Patent

  1. Laubeuf, N., Bhattacharjee, D., & Vrancx, P. (2024). Computer implemented method for transforming a pre trained neural network and a device therefor.
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Book chapters

  1. Bhattacharjee, D., & Chattopadhyay, A. (2023). Synthesis and Technology Mapping for In-Memory Computing. In Emerging Computing: From Devices to Systems (pp. 317–353). Springer. https://doi.org/10.1007/978-981-16-7487-7_10
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  2. Bhattacharjee, D., & Chattopadhyay, A. (2022). Synthesis and Technology Mapping for In-Memory Computing. In Emerging Computing: From Devices to Systems: Looking Beyond Moore and Von Neumann (pp. 317–353). Springer.
  3. Mandal, S., Tavva, Y., Bhattacharjee, D., & Chattopadhyay, A. (2018). ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code. IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip, 128–146. https://doi.org/10.1007/978-3-030-23425-6_7
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  4. Bhattacharjee, D., & Chattopadhyay, A. (2017). In-memory data compression using ReRAMs. In Emerging Technology and Architecture for Big-data Analytics (pp. 275–291). Springer, Cham. https://doi.org/10.1007/978-3-319-54840-1_13
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Journal Publications

  1. Biswal, L., Bhattacharjee, D., Chakrabarti, A., & Chattopadhyay, A. (2024). Synthesis Techniques for Fault-tolerant Quantum Circuit Implementation using the Clifford-group. ACM Transactions on Quantum Computing.
  2. Chattopadhyay, A., Bhattacharjee, D., & Maitra, S. (2023). Improved Linear Decomposition of Majority and Threshold Boolean Functions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. https://doi.org/10.1109/TCAD.2023.3257082
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  3. Yang, S., Bhattacharjee, D., Kumar, V. B. Y., Chatterjee, S., De, S., Debacker, P., Verkest, D., Mallik, A., & Catthoor, F. (2022). AERO: Design Space Exploration Framework for resource-constrained CNN mapping on Tile-based Accelerators. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. https://doi.org/10.1109/JETCAS.2022.3171826
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  4. Laubeuf, N., Doevenspeck, J., Papistas, I. A., Caselli, M., Cosemans, S., Vrancx, P., Bhattacharjee, D., Mallik, A., Debacker, P., Verkest, D., & others. (2022). Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration. ACM Transactions on Design Automation of Electronic Systems (TODAES), 27(5), 1–21. https://doi.org/doi.org/10.1145/3498328
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  5. Houshmand, P., Sarda, G. M., Jain, V., Ueyoshi, K., Papistas, I. A., Shi, M., Zheng, Q., Bhattacharjee, D., Mallik, A., Debacker, P., & others. (2022). DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. IEEE Journal of Solid-State Circuits, 58(1), 203–215.
  6. Bhattacharjee, D., Tavva, Y., Easwaran, A., & Chattopadhyay, A. (2020). Crossbar-constrained technology mapping for reram based in-memory computing. IEEE Transactions on Computers, 69(5), 734–748. https://doi.org/10.1109/TC.2020.2964671
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  7. Biswal, L., Bhattacharjee, D., Chattopadhyay, A., & Rahaman, H. (2019). Techniques for fault-tolerant decomposition of a multicontrolled Toffoli gate. Physical Review A, 100(6), 062326. https://doi.org/10.1103/PhysRevA.100.062326
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  8. Ben-Hur, R., Ronen, R., Haj-Ali, A., Bhattacharjee, D., Eliahu, A., Peled, N., & Kvatinsky, S. (2019). SIMPLER MAGIC: synthesis and mapping of in-memory logic executed in a single row to improve throughput. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. https://doi.org/10.1109/TCAD.2019.2931188
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  9. Siemon, A., Menzel, S., Bhattacharjee, D., Waser, R., Chattopadhyay, A., & Linn, E. (2019). Sklansky tree adder realization in 1S1R resistive switching memory architecture. The European Physical Journal Special Topics, 228(10), 2269–2285. https://doi.org/10.1140/epjst/e2019-900042-x
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  10. Bhattacharjee, D., Kim, W., Chattopadhyay, A., Waser, R., & Rana, V. (2018). Multi-valued and fuzzy logic realization using TaOx memristive devices. Scientific Reports, 8(1), 1–10. https://doi.org/10.1038/s41598-017-18329-3
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  11. Dutta, S., Bhattacharjee, D., & Chattopadhyay, A. (2018). Quantum circuits for Toom-Cook multiplication. Physical Review A, 98(1), 012311.
  12. Bhattacharjee, D., Siemon, A., Linn, E., Menzel, S., & Chattopadhyay, A. (2018). Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays. ACM Journal on Emerging Technologies in Computing Systems (JETC), 14(2), 1–14.
  13. Bhattacharjee, D., Siemon, A., Linn, E., & Chattopadhyay, A. (2017). Efficient complementary resistive switch-based crossbar array booth multiplier. Microelectronics Journal, 64, 78–85.
  14. Bhattacharjee, D., Bakshi, A., & Ghosh, K. (2015). Comparison Between an HVS Inspired Linear Filter and the Bilateral Filter in Performing "Vision at a Glance" through Smoothing with Edge Preservation. International Journal of Image and Graphics, 15(04), 1550015. https://doi.org/10.1142/S0219467815500151
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Conference Publications

  1. Svedas, J., Laubeuf, N., Harvey, R., Singh, A., Man, C., Nada, A., Krishna, T., Myers, J., & Bhattacharjee, D. (2026). Evaluating Cross-Architecture Performance Modeling of Distributed ML Workloads Using StableHLO. Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).
  2. Kundu, J., Bhattacharjee, D., Josephsen, N., Pokhrel, A., De Silva, U., Guo, W., Van Winckel, S., Brebels, S., Herr, Q., Herr, A., & others. (2025). A System Level Performance Evaluation for Superconducting Digital Systems. 2025 Design, Automation & Test in Europe Conference (DATE), 1–7.
  3. Delestrac, P., Battacharjee, D., Yang, S., Moolchandani, D., Catthoor, F., Torres, L., & Novo, D. (2024). Multi-level Analysis of GPU Utilization in ML Training Workloads. 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1–6.
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  4. Delestrac, P., Miquel, J., Bhattacharjee, D., Moolchandani, D., Catthoor, F., Torres, L., & Novo, D. (2024). Analyzing GPU Energy Consumption in Data Movement and Storage. 2024 IEEE 35th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 143–151.
  5. Perumkunnil Komalan, M., Lakshminarasimhan, K., De Silva, U., Bhattacharjee, D., Josephson, T., Herr, Q., & Herr, A. (2024, June). Superconducting Array of Arrays for Acceleration of Transformers (Abstract). 16th Workshop on Low Temperature Electronics (WOLTE16 2024).
  6. Ranga, S., Mao, R., Bhattacharjee, D., Cambria, E., & Chattopadhyay, A. (2024). Rtl agent: An agent-based approach for functionally correct hdl generation via llms. 2024 IEEE 33rd Asian Test Symposium (ATS), 1–6.
  7. Sarda, G. M., Shah, N., Bhattacharjee, D., Debacker, P., & Verhelst, M. (2023, June). HW-Aware Mapping of Graph Neural Networks on RISC-V GPGPU: A Work-in-Progress. Open Source Computer Architecture Research (OSCAR).
  8. Sarda, G. M., Shah, N., Bhattacharjee, D., Debacker, P., & Verhelst, M. (2023). Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis. IEEE International Symposium on Workload Characterization (IISWC), 226–228. https://doi.org/10.1109/IISWC59245.2023.00017
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  9. Caselli, M., Bhattacharjee, D., Mallik, A., Debacker, P., & Verkest, D. (2022). Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation. 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1823–1827.
  10. Ueyoshi, K., Papistas, I. A., Houshmand, P., Sarda, G. M., Jain, V., Shi, M., Zheng, Q., Giraldo, S., Vrancx, P., Doevenspeck, J., & others. (2022). DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. 2022 IEEE International Solid-State Circuits Conference (ISSCC), 65, 1–3. https://doi.org/10.1109/ISSCC42614.2022.9731716
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  11. Bhattacharjee, D., Majumder, A., & Chattopadhyay, A. (2021). In-memory realization of SHA-2 using ReVAMP architecture. 2021 34th International Conference on VLSI Design.
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  12. Bhattacharjee, D., Laubeuf, N., Cosemans, S., Papistas, I., Mallik, A., Debacker, P., Na, M. H., & Verkest, D. (2021). Design-Technology Space Exploration For Energy Efficient AiMC-based Inference Acceleration. IEEE International Symposium on Circuits and Systems (ISCAS).
  13. Houshmand, P., Cosemans, S., Mei, L., Papistas, I., Bhattacharjee, D., Debacker, P., Mallik, A., Verkest, D., & Verhelst, M. (2020). Opportunities and Limitations of Emerging Analog in-Memory Compute DNN Architectures. 2019 IEEE International Electron Devices Meeting (IEDM).
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  14. Dutta, S., Tavva, Y., Bhattacharjee, D., & Chattopadhyay, A. (2020). Efficient Quantum Circuits for Square-Root and Inverse Square-Root. 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), 55–60. https://doi.org/10.1109/VLSID49098.2020.00027
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  15. Bhattacharjee, D., Chattopadhyay, A., Dutta, S., Ronen, R., & Kvatinsky, S. (2020). CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020, 1–9. https://doi.org/10.1145/3400302.3415681
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  16. Tenace, V., Rizzo, R. G., Bhattacharjee, D., Chattopadhyay, A., & Calimera, A. (2019). SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars. 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 372–377.
  17. Bhattacharjee, D., Soeken, M., Dutta, S., Chattopadhyay, A., & De Micheli, G. (2019). Reversible pebble games for reducing qubits in hierarchical quantum circuit synthesis. 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 102–107.
  18. Bhattacharjee, D., Saki, A. A., Alam, M., Chattopadhyay, A., & Ghosh, S. (2019). MUQUT: Multi-Constraint Quantum Circuit Mapping on Noisy Intermediate-Scale Quantum Computers. ArXiv Preprint ArXiv:1911.08559.
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  19. Bhattacharjee, D., Chattopadhyay, A., & Liwongan, R. J. (2019). Accelerating Binary-Matrix Multiplication on FPGA. 2019 32nd IEEE International System-on-Chip Conference (SOCC), 254–259.
  20. Vatwani, T., Dutt, A., Bhattacharjee, D., & Chattopadhyay, A. (2018). Floating point multiplication mapping on ReRAM based in-memory computing architecture. 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), 439–444.
  21. Bhattacharjee, D., Amaŕu, L., & Chattopadhyay, A. (2018). Technology-aware logic synthesis for ReRAM based in-memory computing. 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1435–1440.
  22. Surhonne, A. P., Bhattacharjee, D., & Chattopadhyay, A. (2018). Synthesis of multi-valued literal using Lukasiewicz logic. 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), 204–209.
  23. Bhattacharjee, D., & Chattopadhyay, A. (2018). Synthesis, Technology Mapping and Optimization for Emerging Technologies. 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 369–374.
  24. Bhattacharjee, D., Dutt, A., & Chattopadhyay, A. (2018). MAMI: Majority and Multi-Input Logic on Memristive Crossbar Array. 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 435–438.
  25. Mandal, S., Bhattacharjee, D., Tavva, Y., & Chattopadhyay, A. (2018). ReRAM-based in-memory computation of galois field arithmetic. 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 1–6.
  26. Bhattacharjee, D., Easwaran, A., & Chattopadhyay, A. (2017). Area-constrained technology mapping for in-memory computing using reram devices. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 69–74.
  27. Bhattacharjee, D., & Chattopadhyay, A. (2017). Efficient binary basic linear algebra operations on reram crossbar arrays. 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 277–282.
  28. Bhattacharjee, D., Devadoss, R., & Chattopadhyay, A. (2017). ReVAMP: ReRAM based VLIW architecture for in-memory computing. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 782–787.
  29. Bhattacharjee, D., Pudi, V., & Chattopadhyay, A. (2017). SHA-3 implementation using ReRAM based in-memory computing architecture. 2017 18th International Symposium on Quality Electronic Design (ISQED), 325–330.
  30. Bhattacharjee, D., Chattopadhyay, S., & Banerjee, A. (2016). EAST: efficient assertion simulation techniques. 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1363–1368.
  31. Bhattacharjee, D., & Chattopadhyay, A. (2016). Hardware Accelerator for Stream Cipher Spritz. Proceedings of the 13th International Joint Conference on e-Business and Telecommunications, 215–222.
  32. Bhattacharjee, D., & Bhattacharya, P. (2016). Ensemble Classifier based approach for Code-Mixed Cross-Script Question Classification. Working Notes of {FIRE} 2016 - Forum for Information Retrieval Evaluation, Kolkata, India, December 7-10, 2016., 1737, 119–121.
  33. Bhattacharjee, D., & Chattopadhyay, A. (2016). Delay-optimal technology mapping for in-memory computing using ReRAM devices. 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1–6.
  34. Bhattacharjee, D., Siemon, A., Linn, E., Menzel, S., & Chattopadhyay, A. (2016). Efficient implementation of multiplexer and priority multiplexer using 1S1R ReRAM crossbar arrays. 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 1–4.
  35. Bhattacharjee, D., Merchant, F., & Chattopadhyay, A. (2016). Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays. 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 1–6.
  36. Bhattacharjee, D., Siemon, A., Linn, E., Menzel, S., & Chattopadhyay, A. (2016). Fast comparator implementation using 1S1R ReRAM crossbar arrays. APCCAS.
  37. Bhattacharjee, D., Banerjee, A., & Chattopadhyay, A. (2015). Evodeb: Debugging evolving hardware designs. 2015 28th International Conference on VLSI Design, 481–486.
  38. Bhattacharjee, D., & Chattopadhyay, A. (2014). Efficient hardware accelerator for AEGIS-128 authenticated encryption. International Conference on Information Security and Cryptology, 385–402.

Pre-prints

  1. Svedas, J., Watson, H., Laubeuf, N., Moolchandani, D., Nada, A., Singh, A., Biswas, D., Myers, J., & Bhattacharjee, D. (2025). A Survey of End-to-End Modeling for Distributed DNN Training: Workloads, Simulators, and TCO. ArXiv Preprint ArXiv:2506.09275.
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  2. Altayo, J., Delestrac, P., Novo, D., Yang, S., Bhattacharjee, D., & Catthoor, F. (2025). Addressing memory bandwidth scalability in vector processors for streaming applications. ArXiv Preprint ArXiv:2505.12856.
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  3. Chattopadhyay, A., Bhattacharjee, D., & Maitra, S. (2025). Linear Decomposition of the Majority Boolean Function using the Ones on Smaller Variables. ArXiv Preprint ArXiv:2504.03262.
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  4. Bhattacharjee, D., Marinelli, T., Pathak, K., & Kourzanov, P. (2024). Full-stack evaluation of Machine Learning inference workloads for RISC-V systems. RISC-V Summit Europe 2024. https://doi.org/10.48550/arXiv.2405.15380
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  5. Chen, Y., Yang, S., Bhattacharjee, D., Catthoor, F., & Mallik, A. (2024). SAfEPaTh: A System-Level Approach for Efficient Power and Thermal Estimation of Convolutional Neural Network Accelerator. ArXiv Preprint ArXiv:2407.17623.
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  6. Bhattacharjee, D., & Chattopadhyay, A. (2017). Depth-optimal quantum circuit placement for arbitrary topologies. ArXiv Preprint ArXiv:1703.08540.
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Thesis

  1. Bhattacharjee, D. (2018). Architectures and automation for beyond-CMOS technologies [PhD thesis].
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  2. Bhattacharjee, D. (2015). New Advances in Verification and Debugging of Hardware Systems. Indian Statistical Institute, Kolkata.
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