Publications

Patent

Laubeuf, N., Bhattacharjee, D., & Vrancx, P. (2024). Computer implemented method for transforming a pre trained neural network and a device therefor.
```
@misc{laubeuf2024computer,
  title = {Computer implemented method for transforming a pre trained neural network and a device therefor},
  author = {Laubeuf, Nathan and Bhattacharjee, Debjyoti and Vrancx, Peter},
  year = {2024},
  month = feb,
  note = {US Patent App. 18/228,153},
  link = {https://patentimages.storage.googleapis.com/26/e9/ef/6987f2d6456a2b/US20240046098A1.pdf}
}
```

Book chapters

Bhattacharjee, D., & Chattopadhyay, A. (2023). Synthesis and Technology Mapping for In-Memory Computing. In Emerging Computing: From Devices to Systems (pp. 317–353). Springer. https://doi.org/10.1007/978-981-16-7487-7_10
```
@incollection{bhattacharjee2023synthesis,
  title = {Synthesis and Technology Mapping for In-Memory Computing},
  author = {Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  booktitle = {Emerging Computing: From Devices to Systems},
  pages = {317--353},
  year = {2023},
  publisher = {Springer},
  doi = {10.1007/978-981-16-7487-7_10}
}
```
Bhattacharjee, D., & Chattopadhyay, A. (2022). Synthesis and Technology Mapping for In-Memory Computing. In Emerging Computing: From Devices to Systems: Looking Beyond Moore and Von Neumann (pp. 317–353). Springer.
```
@incollection{bhattacharjee2022synthesis,
  title = {Synthesis and Technology Mapping for In-Memory Computing},
  author = {Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  booktitle = {Emerging Computing: From Devices to Systems: Looking Beyond Moore and Von Neumann},
  pages = {317--353},
  year = {2022},
  publisher = {Springer}
}
```
Mandal, S., Tavva, Y., Bhattacharjee, D., & Chattopadhyay, A. (2018). ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code. IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip, 128–146. https://doi.org/10.1007/978-3-030-23425-6_7
```
@inproceedings{mandal2018reram,
  title = {ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code},
  author = {Mandal, Swagata and Tavva, Yaswanth and Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  booktitle = {IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip},
  pages = {128--146},
  year = {2018},
  organization = {Springer, Cham},
  doi = {10.1007/978-3-030-23425-6_7}
}
```
Bhattacharjee, D., & Chattopadhyay, A. (2017). In-memory data compression using ReRAMs. In Emerging Technology and Architecture for Big-data Analytics (pp. 275–291). Springer, Cham. https://doi.org/10.1007/978-3-319-54840-1_13
```
@incollection{bhattacharjee2017memory,
  title = {In-memory data compression using ReRAMs},
  author = {Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  booktitle = {Emerging Technology and Architecture for Big-data Analytics},
  pages = {275--291},
  year = {2017},
  publisher = {Springer, Cham},
  doi = {10.1007/978-3-319-54840-1_13}
}
```

Journal Publications

Chattopadhyay, A., Bhattacharjee, D., & Maitra, S. (2023). Improved Linear Decomposition of Majority and Threshold Boolean Functions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. https://doi.org/10.1109/TCAD.2023.3257082
```
@article{chat2023,
  title = {Improved Linear Decomposition of Majority and Threshold Boolean Functions},
  author = {Chattopadhyay, Anupam and Bhattacharjee, Debjyoti and Maitra, Subhamoy},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year = {2023},
  publisher = {IEEE},
  code = {https://github.com/debjyoti0891/crumbly-majority},
  doi = {10.1109/TCAD.2023.3257082 }
}
```
Yang, S., Bhattacharjee, D., Kumar, V. B. Y., Chatterjee, S., De, S., Debacker, P., Verkest, D., Mallik, A., & Catthoor, F. (2022). AERO: Design Space Exploration Framework for resource-constrained CNN mapping on Tile-based Accelerators. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. https://doi.org/10.1109/JETCAS.2022.3171826
```
@article{yang2022aero,
  title = {AERO: Design Space Exploration Framework for resource-constrained CNN mapping on Tile-based Accelerators},
  author = {Yang, Simei and Bhattacharjee, Debjyoti and Kumar, Vinay BY and Chatterjee, Saikat and De, Sayandip and Debacker, Peter and Verkest, Diederik and Mallik, Arindam and Catthoor, Francky},
  journal = {IEEE Journal on Emerging and Selected Topics in Circuits and Systems},
  year = {2022},
  publisher = {IEEE},
  doi = {10.1109/JETCAS.2022.3171826}
}
```
Laubeuf, N., Doevenspeck, J., Papistas, I. A., Caselli, M., Cosemans, S., Vrancx, P., Bhattacharjee, D., Mallik, A., Debacker, P., Verkest, D., & others. (2022). Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration. ACM Transactions on Design Automation of Electronic Systems (TODAES), 27(5), 1–21. https://doi.org/doi.org/10.1145/3498328
```
@article{laubeuf2022dynamic,
  title = {Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration},
  author = {Laubeuf, Nathan and Doevenspeck, Jonas and Papistas, Ioannis A and Caselli, Michele and Cosemans, Stefan and Vrancx, Peter and Bhattacharjee, Debjyoti and Mallik, Arindam and Debacker, Peter and Verkest, Diederik and others},
  journal = {ACM Transactions on Design Automation of Electronic Systems (TODAES)},
  volume = {27},
  number = {5},
  pages = {1--21},
  year = {2022},
  publisher = {ACM New York, NY},
  doi = {doi.org/10.1145/3498328}
}
```
Houshmand, P., Sarda, G. M., Jain, V., Ueyoshi, K., Papistas, I. A., Shi, M., Zheng, Q., Bhattacharjee, D., Mallik, A., Debacker, P., & others. (2022). DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. IEEE Journal of Solid-State Circuits, 58(1), 203–215.
```
@article{houshmand2022diana,
  title = {DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge},
  author = {Houshmand, Pouya and Sarda, Giuseppe M and Jain, Vikram and Ueyoshi, Kodai and Papistas, Ioannis A and Shi, Man and Zheng, Qilin and Bhattacharjee, Debjyoti and Mallik, Arindam and Debacker, Peter and others},
  journal = {IEEE Journal of Solid-State Circuits},
  volume = {58},
  number = {1},
  pages = {203--215},
  year = {2022},
  publisher = {IEEE}
}
```

Bhattacharjee, D., Tavva, Y., Easwaran, A., & Chattopadhyay, A. (2020). Crossbar-constrained technology mapping for reram based in-memory computing. IEEE Transactions on Computers, 69(5), 734–748. https://doi.org/10.1109/TC.2020.2964671

@article{bhattacharjee2020crossbar,
  title = {Crossbar-constrained technology mapping for reram based in-memory computing},
  author = {Bhattacharjee, Debjyoti and Tavva, Yaswanth and Easwaran, Arvind and Chattopadhyay, Anupam},
  journal = {IEEE Transactions on Computers},
  volume = {69},
  number = {5},
  pages = {734--748},
  year = {2020},
  publisher = {IEEE},
  code = {https://github.com/debjyoti0891/arche},
  doi = {10.1109/TC.2020.2964671},
  link = {https://arxiv.org/pdf/1809.08195.pdf}
}

Biswal, L., Bhattacharjee, D., Chattopadhyay, A., & Rahaman, H. (2019). Techniques for fault-tolerant decomposition of a multicontrolled Toffoli gate. Physical Review A, 100(6), 062326. https://doi.org/10.1103/PhysRevA.100.062326
```
@article{biswal2019techniques,
  title = {Techniques for fault-tolerant decomposition of a multicontrolled Toffoli gate},
  author = {Biswal, Laxmidhar and Bhattacharjee, Debjyoti and Chattopadhyay, Anupam and Rahaman, Hafizur},
  journal = {Physical Review A},
  volume = {100},
  number = {6},
  pages = {062326},
  year = {2019},
  publisher = {American Physical Society},
  doi = {10.1103/PhysRevA.100.062326},
  link = {https://arxiv.org/pdf/1904.06920.pdf}
}
```
Ben-Hur, R., Ronen, R., Haj-Ali, A., Bhattacharjee, D., Eliahu, A., Peled, N., & Kvatinsky, S. (2019). SIMPLER MAGIC: synthesis and mapping of in-memory logic executed in a single row to improve throughput. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. https://doi.org/10.1109/TCAD.2019.2931188
```
@article{ben2019simpler,
  title = {SIMPLER MAGIC: synthesis and mapping of in-memory logic executed in a single row to improve throughput},
  author = {Ben-Hur, Rotem and Ronen, Ronny and Haj-Ali, Ameer and Bhattacharjee, Debjyoti and Eliahu, Adi and Peled, Natan and Kvatinsky, Shahar},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year = {2019},
  publisher = {IEEE},
  code = {https://github.com/debjyoti0891/arche},
  doi = {10.1109/TCAD.2019.2931188}
}
```
Siemon, A., Menzel, S., Bhattacharjee, D., Waser, R., Chattopadhyay, A., & Linn, E. (2019). Sklansky tree adder realization in 1S1R resistive switching memory architecture. The European Physical Journal Special Topics, 228(10), 2269–2285. https://doi.org/10.1140/epjst/e2019-900042-x
```
@article{siemon2019sklansky,
  title = {Sklansky tree adder realization in 1S1R resistive switching memory architecture},
  author = {Siemon, Anne and Menzel, Stephan and Bhattacharjee, Debjyoti and Waser, Rainer and Chattopadhyay, Anupam and Linn, Eike},
  journal = {The European Physical Journal Special Topics},
  volume = {228},
  number = {10},
  pages = {2269--2285},
  year = {2019},
  publisher = {Springer Berlin Heidelberg},
  doi = {10.1140/epjst/e2019-900042-x}
}
```

Bhattacharjee, D., Kim, W., Chattopadhyay, A., Waser, R., & Rana, V. (2018). Multi-valued and fuzzy logic realization using TaOx memristive devices. Scientific Reports, 8(1), 1–10. https://doi.org/10.1038/s41598-017-18329-3

@article{bhattacharjee2018multi,
  title = {Multi-valued and fuzzy logic realization using TaOx memristive devices},
  author = {Bhattacharjee, Debjyoti and Kim, Wonjoo and Chattopadhyay, Anupam and Waser, Rainer and Rana, Vikas},
  journal = {Scientific reports},
  volume = {8},
  number = {1},
  pages = {1--10},
  year = {2018},
  publisher = {Nature Publishing Group},
  doi = {10.1038/s41598-017-18329-3},
  link = {https://www.nature.com/articles/s41598-017-18329-3.pdf}
}

Dutta, S., Bhattacharjee, D., & Chattopadhyay, A. (2018). Quantum circuits for Toom-Cook multiplication. Physical Review A, 98(1), 012311.
```
@article{dutta2018quantum,
  title = {Quantum circuits for Toom-Cook multiplication},
  author = {Dutta, Srijit and Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  journal = {Physical Review A},
  volume = {98},
  number = {1},
  pages = {012311},
  year = {2018},
  publisher = {American Physical Society}
}
```
Bhattacharjee, D., Siemon, A., Linn, E., Menzel, S., & Chattopadhyay, A. (2018). Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays. ACM Journal on Emerging Technologies in Computing Systems (JETC), 14(2), 1–14.
```
@article{bhattacharjee2018kogge,
  title = {Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays},
  author = {Bhattacharjee, Debjyoti and Siemon, Anne and Linn, Eike and Menzel, Stephan and Chattopadhyay, Anupam},
  journal = {ACM Journal on Emerging Technologies in Computing Systems (JETC)},
  volume = {14},
  number = {2},
  pages = {1--14},
  year = {2018},
  publisher = {ACM New York, NY, USA}
}
```
Bhattacharjee, D., Siemon, A., Linn, E., & Chattopadhyay, A. (2017). Efficient complementary resistive switch-based crossbar array booth multiplier. Microelectronics Journal, 64, 78–85.
```
@article{bhattacharjee2017efficient,
  title = {Efficient complementary resistive switch-based crossbar array booth multiplier},
  author = {Bhattacharjee, Debjyoti and Siemon, Anne and Linn, Eike and Chattopadhyay, Anupam},
  journal = {Microelectronics Journal},
  volume = {64},
  pages = {78--85},
  year = {2017},
  publisher = {Elsevier}
}
```
Bhattacharjee, D., Bakshi, A., & Ghosh, K. (2015). Comparison Between an HVS Inspired Linear Filter and the Bilateral Filter in Performing "Vision at a Glance" through Smoothing with Edge Preservation. International Journal of Image and Graphics, 15(04), 1550015. https://doi.org/10.1142/S0219467815500151
```
@article{bhattacharjee2015comparison,
  title = {Comparison Between an HVS Inspired Linear Filter and the Bilateral Filter in Performing "Vision at a Glance" through Smoothing with Edge Preservation},
  author = {Bhattacharjee, Debjyoti and Bakshi, Ashish and Ghosh, Kuntal},
  journal = {International Journal of Image and Graphics},
  volume = {15},
  number = {04},
  pages = {1550015},
  year = {2015},
  doi = {10.1142/S0219467815500151}
}
```

Conference Publications

Caselli, M., Bhattacharjee, D., Mallik, A., Debacker, P., & Verkest, D. (2022). Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation. 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1823–1827.
```
@inproceedings{caselli2022tiny,
  title = {Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation},
  author = {Caselli, Michele and Bhattacharjee, Debjyoti and Mallik, Arindam and Debacker, Peter and Verkest, Diederik},
  booktitle = {2022 IEEE International Symposium on Circuits and Systems (ISCAS)},
  pages = {1823--1827},
  year = {2022},
  organization = {IEEE}
}
```
Ueyoshi, K., Papistas, I. A., Houshmand, P., Sarda, G. M., Jain, V., Shi, M., Zheng, Q., Giraldo, S., Vrancx, P., Doevenspeck, J., & others. (2022). DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. 2022 IEEE International Solid-State Circuits Conference (ISSCC), 65, 1–3. https://doi.org/10.1109/ISSCC42614.2022.9731716
```
@inproceedings{ueyoshi2022diana,
  title = {DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC},
  author = {Ueyoshi, Kodai and Papistas, Ioannis A and Houshmand, Pouya and Sarda, Giuseppe M and Jain, Vikram and Shi, Man and Zheng, Qilin and Giraldo, Sebastian and Vrancx, Peter and Doevenspeck, Jonas and others},
  booktitle = {2022 IEEE International Solid-State Circuits Conference (ISSCC)},
  volume = {65},
  pages = {1--3},
  year = {2022},
  organization = {IEEE},
  doi = {10.1109/ISSCC42614.2022.9731716}
}
```
Bhattacharjee, D., Majumder, A., & Chattopadhyay, A. (2021). In-memory realization of SHA-2 using ReVAMP architecture. 2021 34th International Conference on VLSI Design.
```
@inproceedings{bhattacharjee2021sha,
  title = {In-memory realization of SHA-2 using ReVAMP architecture},
  author = {Bhattacharjee, Debjyoti and Majumder, Anirban and Chattopadhyay, Anupam},
  booktitle = {2021 34th International Conference on VLSI Design},
  pages = {},
  year = {2021},
  organization = {IEEE},
  code = {https://github.com/debjyoti0891/arche}
}
```
Bhattacharjee, D., Laubeuf, N., Cosemans, S., Papistas, I., Mallik, A., Debacker, P., Na, M. H., & Verkest, D. (2021). Design-Technology Space Exploration For Energy Efficient AiMC-based Inference Acceleration. IEEE International Symposium on Circuits and Systems (ISCAS).
```
@inproceedings{iscas201,
  title = {Design-Technology Space Exploration For Energy
  Efficient AiMC-based Inference Acceleration},
  author = {Bhattacharjee, Debjyoti and Laubeuf, Nathan and Cosemans, Stefan and Papistas, Ioannis and Mallik, Arindam and Debacker, Peter and Na, Myung Hee and Verkest, Diederik},
  booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
  year = {2021},
  organization = {IEEE}
}
```
Houshmand, P., Cosemans, S., Mei, L., Papistas, I., Bhattacharjee, D., Debacker, P., Mallik, A., Verkest, D., & Verhelst, M. (2020). Opportunities and Limitations of Emerging Analog in-Memory Compute DNN Architectures. 2019 IEEE International Electron Devices Meeting (IEDM).
```
@inproceedings{iedm2020,
  title = {Opportunities and Limitations of Emerging Analog in-Memory Compute DNN Architectures},
  author = {Houshmand, Pouya and Cosemans, Stefan and Mei, Linyan and Papistas, Ioannis and Bhattacharjee, Debjyoti and Debacker, Peter and Mallik, Arindam and Verkest, Diederik and Verhelst, Marian},
  booktitle = {2019 IEEE International Electron Devices Meeting (IEDM)},
  year = {2020},
  organization = {IEEE},
  code = {https://github.com/ZigZag-Project/zigzag}
}
```
Dutta, S., Tavva, Y., Bhattacharjee, D., & Chattopadhyay, A. (2020). Efficient Quantum Circuits for Square-Root and Inverse Square-Root. 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), 55–60. https://doi.org/10.1109/VLSID49098.2020.00027
```
@inproceedings{dutta2020efficient,
  title = {Efficient Quantum Circuits for Square-Root and Inverse Square-Root},
  author = {Dutta, Srijit and Tavva, Yaswanth and Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  booktitle = {2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID)},
  pages = {55--60},
  year = {2020},
  organization = {IEEE},
  code = {https://github.com/debjyoti0891/QuantumSqRoot},
  doi = {10.1109/VLSID49098.2020.00027}
}
```

Bhattacharjee, D., Chattopadhyay, A., Dutta, S., Ronen, R., & Kvatinsky, S. (2020). CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020, 1–9. https://doi.org/10.1145/3400302.3415681

@inproceedings{DBLP:conf/iccad/BhattacharjeeCD20,
  author = {Bhattacharjee, Debjyoti and Chattopadhyay, Anupam and Dutta, Srijit and Ronen, Ronny and Kvatinsky, Shahar},
  title = {{CONTRA:} Area-Constrained Technology Mapping Framework For Memristive
                 Memory Processing Unit},
  booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
                 2020, San Diego, CA, USA, November 2-5, 2020},
  pages = {1--9},
  publisher = {{IEEE}},
  year = {2020},
  doi = {10.1145/3400302.3415681},
  code = {https://github.com/debjyoti0891/arche},
  link = {https://arxiv.org/pdf/2009.00881.pdf},
  timestamp = {Wed, 02 Dec 2020 13:55:39 +0100},
  biburl = {https://dblp.org/rec/conf/iccad/BhattacharjeeCD20.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

Tenace, V., Rizzo, R. G., Bhattacharjee, D., Chattopadhyay, A., & Calimera, A. (2019). SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars. 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 372–377.
```
@inproceedings{tenace2019said,
  title = {SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars},
  author = {Tenace, Valerio and Rizzo, Roberto G and Bhattacharjee, Debjyoti and Chattopadhyay, Anupam and Calimera, Andrea},
  booktitle = {2019 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
  pages = {372--377},
  year = {2019},
  organization = {IEEE}
}
```
Bhattacharjee, D., Soeken, M., Dutta, S., Chattopadhyay, A., & De Micheli, G. (2019). Reversible pebble games for reducing qubits in hierarchical quantum circuit synthesis. 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 102–107.
```
@inproceedings{bhattacharjee2019reversible,
  title = {Reversible pebble games for reducing qubits in hierarchical quantum circuit synthesis},
  author = {Bhattacharjee, Debjyoti and Soeken, Mathias and Dutta, Srijit and Chattopadhyay, Anupam and De Micheli, Giovanni},
  booktitle = {2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)},
  pages = {102--107},
  year = {2019},
  organization = {IEEE}
}
```
Bhattacharjee, D., Saki, A. A., Alam, M., Chattopadhyay, A., & Ghosh, S. (2019). MUQUT: Multi-Constraint Quantum Circuit Mapping on Noisy Intermediate-Scale Quantum Computers. ArXiv Preprint ArXiv:1911.08559.
```
@article{bhattacharjee2019muqut,
  title = {MUQUT: Multi-Constraint Quantum Circuit Mapping on Noisy Intermediate-Scale Quantum Computers},
  author = {Bhattacharjee, Debjyoti and Saki, Abdullah Ash and Alam, Mahabubul and Chattopadhyay, Anupam and Ghosh, Swaroop},
  journal = {arXiv preprint arXiv:1911.08559},
  year = {2019},
  code = {https://github.com/debjyoti0891/quantum-chain/},
  link = {https://arxiv.org/pdf/1911.08559.pdf}
}
```
Bhattacharjee, D., Chattopadhyay, A., & Liwongan, R. J. (2019). Accelerating Binary-Matrix Multiplication on FPGA. 2019 32nd IEEE International System-on-Chip Conference (SOCC), 254–259.
```
@inproceedings{bhattacharjee2019accelerating,
  title = {Accelerating Binary-Matrix Multiplication on FPGA},
  author = {Bhattacharjee, Debjyoti and Chattopadhyay, Anupam and Liwongan, Ricardo Jack},
  booktitle = {2019 32nd IEEE International System-on-Chip Conference (SOCC)},
  pages = {254--259},
  year = {2019},
  organization = {IEEE}
}
```
Vatwani, T., Dutt, A., Bhattacharjee, D., & Chattopadhyay, A. (2018). Floating point multiplication mapping on reram based in-memory computing architecture. 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), 439–444.
```
@inproceedings{vatwani2018floating,
  title = {Floating point multiplication mapping on reram based in-memory computing architecture},
  author = {Vatwani, Tarun and Dutt, Arko and Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  booktitle = {2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)},
  pages = {439--444},
  year = {2018},
  organization = {IEEE}
}
```
Bhattacharjee, D., Amaŕu, L., & Chattopadhyay, A. (2018). Technology-aware logic synthesis for ReRAM based in-memory computing. 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1435–1440.
```
@inproceedings{bhattacharjee2018technology,
  title = {Technology-aware logic synthesis for ReRAM based in-memory computing},
  author = {Bhattacharjee, Debjyoti and Ama{\'r}u, Luca and Chattopadhyay, Anupam},
  booktitle = {2018 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
  pages = {1435--1440},
  year = {2018},
  organization = {IEEE}
}
```
Surhonne, A. P., Bhattacharjee, D., & Chattopadhyay, A. (2018). Synthesis of multi-valued literal using Lukasiewicz logic. 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), 204–209.
```
@inproceedings{surhonne2018synthesis,
  title = {Synthesis of multi-valued literal using Lukasiewicz logic},
  author = {Surhonne, Anmol Prakash and Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  booktitle = {2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL)},
  pages = {204--209},
  year = {2018},
  organization = {IEEE}
}
```
Bhattacharjee, D., & Chattopadhyay, A. (2018). Synthesis, Technology Mapping and Optimization for Emerging Technologies. 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 369–374.
```
@inproceedings{bhattacharjee2018synthesis,
  title = {Synthesis, Technology Mapping and Optimization for Emerging Technologies},
  author = {Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  booktitle = {2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
  pages = {369--374},
  year = {2018},
  organization = {IEEE}
}
```
Bhattacharjee, D., Dutt, A., & Chattopadhyay, A. (2018). MAMI: Majority and Multi-Input Logic on Memristive Crossbar Array. 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 435–438.
```
@inproceedings{bhattacharjee2018mami,
  title = {MAMI: Majority and Multi-Input Logic on Memristive Crossbar Array},
  author = {Bhattacharjee, Debjyoti and Dutt, Arko and Chattopadhyay, Anupam},
  booktitle = {2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)},
  pages = {435--438},
  year = {2018},
  organization = {IEEE}
}
```
Mandal, S., Bhattacharjee, D., Tavva, Y., & Chattopadhyay, A. (2018). ReRAM-based in-memory computation of galois field arithmetic. 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 1–6.
```
@inproceedings{mandal2018reram,
  title = {ReRAM-based in-memory computation of galois field arithmetic},
  author = {Mandal, Swagata and Bhattacharjee, Debjyoti and Tavva, Yaswanth and Chattopadhyay, Anupam},
  booktitle = {2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)},
  pages = {1--6},
  year = {2018},
  organization = {IEEE}
}
```
Bhattacharjee, D., Easwaran, A., & Chattopadhyay, A. (2017). Area-constrained technology mapping for in-memory computing using reram devices. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 69–74.
```
@inproceedings{bhattacharjee2017area,
  title = {Area-constrained technology mapping for in-memory computing using reram devices},
  author = {Bhattacharjee, Debjyoti and Easwaran, Arvind and Chattopadhyay, Anupam},
  booktitle = {2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)},
  pages = {69--74},
  year = {2017},
  organization = {IEEE}
}
```
Bhattacharjee, D., & Chattopadhyay, A. (2017). Efficient binary basic linear algebra operations on reram crossbar arrays. 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 277–282.
```
@inproceedings{bhattacharjee2017efficient,
  title = {Efficient binary basic linear algebra operations on reram crossbar arrays},
  author = {Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  booktitle = {2017 30th international conference on VLSI design and 2017 16th international conference on embedded systems (VLSID)},
  pages = {277--282},
  year = {2017},
  organization = {IEEE}
}
```
Bhattacharjee, D., Devadoss, R., & Chattopadhyay, A. (2017). ReVAMP: ReRAM based VLIW architecture for in-memory computing. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 782–787.
```
@inproceedings{bhattacharjee2017revamp,
  title = {ReVAMP: ReRAM based VLIW architecture for in-memory computing},
  author = {Bhattacharjee, Debjyoti and Devadoss, Rajeswari and Chattopadhyay, Anupam},
  booktitle = {Design, Automation \& Test in Europe Conference \& Exhibition (DATE), 2017},
  pages = {782--787},
  year = {2017},
  organization = {IEEE}
}
```
Bhattacharjee, D., Pudi, V., & Chattopadhyay, A. (2017). SHA-3 implementation using ReRAM based in-memory computing architecture. 2017 18th International Symposium on Quality Electronic Design (ISQED), 325–330.
```
@inproceedings{bhattacharjee2017sha,
  title = {SHA-3 implementation using ReRAM based in-memory computing architecture},
  author = {Bhattacharjee, Debjyoti and Pudi, Vikramkumar and Chattopadhyay, Anupam},
  booktitle = {2017 18th International Symposium on Quality Electronic Design (ISQED)},
  pages = {325--330},
  year = {2017},
  organization = {IEEE}
}
```
Bhattacharjee, D., Chattopadhyay, S., & Banerjee, A. (2016). EAST: efficient assertion simulation techniques. 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1363–1368.
```
@inproceedings{bhattacharjee2016east,
  title = {EAST: efficient assertion simulation techniques},
  author = {Bhattacharjee, Debjyoti and Chattopadhyay, Soumi and Banerjee, Ansuman},
  booktitle = {2016 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
  pages = {1363--1368},
  year = {2016},
  organization = {IEEE}
}
```
Bhattacharjee, D., & Chattopadhyay, A. (2016). Hardware Accelerator for Stream Cipher Spritz. Proceedings of the 13th International Joint Conference on e-Business and Telecommunications, 215–222.
```
@inproceedings{bhattacharjee2016hardware,
  title = {Hardware Accelerator for Stream Cipher Spritz},
  author = {Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  booktitle = {Proceedings of the 13th International Joint Conference on e-Business and Telecommunications},
  pages = {215--222},
  year = {2016}
}
```
Bhattacharjee, D., & Bhattacharya, P. (2016). Ensemble Classifier based approach for Code-Mixed Cross-Script Question Classification. Working Notes of {FIRE} 2016 - Forum for Information Retrieval Evaluation, Kolkata, India, December 7-10, 2016., 1737, 119–121.
```
@inproceedings{bhattacharjee2016ensemble,
  title = {Ensemble Classifier based approach for Code-Mixed Cross-Script Question Classification},
  author = {Bhattacharjee, Debjyoti and Bhattacharya, Paheli},
  booktitle = {Working notes of $\{$FIRE$\}$ 2016 - Forum for Information Retrieval Evaluation, Kolkata, India, December 7-10, 2016.},
  volume = {1737},
  pages = {119--121},
  year = {2016},
  organization = {CEUR-WS.org}
}
```
Bhattacharjee, D., & Chattopadhyay, A. (2016). Delay-optimal technology mapping for in-memory computing using ReRAM devices. 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1–6.
```
@inproceedings{bhattacharjee2016delay,
  title = {Delay-optimal technology mapping for in-memory computing using ReRAM devices},
  author = {Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  booktitle = {2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
  pages = {1--6},
  year = {2016},
  organization = {IEEE}
}
```
Bhattacharjee, D., Siemon, A., Linn, E., Menzel, S., & Chattopadhyay, A. (2016). Efficient implementation of multiplexer and priority multiplexer using 1S1R ReRAM crossbar arrays. 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 1–4.
```
@inproceedings{bhattacharjee2016efficient,
  title = {Efficient implementation of multiplexer and priority multiplexer using 1S1R ReRAM crossbar arrays},
  author = {Bhattacharjee, Debjyoti and Siemon, Anne and Linn, Eike and Menzel, Stephan and Chattopadhyay, Anupam},
  booktitle = {2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)},
  pages = {1--4},
  year = {2016},
  organization = {IEEE}
}
```
Bhattacharjee, D., Merchant, F., & Chattopadhyay, A. (2016). Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays. 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 1–6.
```
@inproceedings{bhattacharjee2016enabling,
  title = {Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays},
  author = {Bhattacharjee, Debjyoti and Merchant, Farhad and Chattopadhyay, Anupam},
  booktitle = {2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)},
  pages = {1--6},
  year = {2016},
  organization = {IEEE}
}
```
Bhattacharjee, D., Siemon, A., Linn, E., Menzel, S., & Chattopadhyay, A. (2016). Fast comparator implementation using 1S1R ReRAM crossbar arrays. APCCAS.
```
@inproceedings{bhattacharjeefast,
  title = {Fast comparator implementation using 1S1R ReRAM crossbar arrays},
  author = {Bhattacharjee, Debjyoti and Siemon, Anne and Linn, Eike and Menzel, Stephan and Chattopadhyay, Anupam},
  booktitle = {APCCAS},
  year = {2016}
}
```
Bhattacharjee, D., Banerjee, A., & Chattopadhyay, A. (2015). Evodeb: Debugging evolving hardware designs. 2015 28th International Conference on VLSI Design, 481–486.
```
@inproceedings{bhattacharjee2015evodeb,
  title = {Evodeb: Debugging evolving hardware designs},
  author = {Bhattacharjee, Debjyoti and Banerjee, Ansuman and Chattopadhyay, Anupam},
  booktitle = {2015 28th International Conference on VLSI Design},
  pages = {481--486},
  year = {2015},
  organization = {IEEE}
}
```
Bhattacharjee, D., & Chattopadhyay, A. (2014). Efficient hardware accelerator for AEGIS-128 authenticated encryption. International Conference on Information Security and Cryptology, 385–402.
```
@inproceedings{bhattacharjee2014efficient,
  title = {Efficient hardware accelerator for AEGIS-128 authenticated encryption},
  author = {Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  booktitle = {International Conference on Information Security and Cryptology},
  pages = {385--402},
  year = {2014},
  organization = {Springer, Cham}
}
```

Pre-prints

Bhattacharjee, D., & Chattopadhyay, A. (2017). Depth-optimal quantum circuit placement for arbitrary topologies. ArXiv Preprint ArXiv:1703.08540.
```
@article{bhattacharjee2017depth,
  title = {Depth-optimal quantum circuit placement for arbitrary topologies},
  author = {Bhattacharjee, Debjyoti and Chattopadhyay, Anupam},
  journal = {arXiv preprint arXiv:1703.08540},
  year = {2017},
  link = {https://arxiv.org/pdf/1703.08540.pdf}
}
```

Thesis

Bhattacharjee, D. (2018). Architectures and automation for beyond-CMOS technologies [PhD thesis].
```
@phdthesis{bhattacharjee2018architectures,
  title = {Architectures and automation for beyond-CMOS technologies},
  author = {Bhattacharjee, Debjyoti},
  year = {2018},
  link = {10.32657/10220/47437}
}
```
Bhattacharjee, D. (2015). New Advances in Verification and Debugging of Hardware Systems. Indian Statistical Institute, Kolkata.
```
@masterthesis{bhattacharjee2015new,
  title = {New Advances in Verification and Debugging of Hardware Systems},
  author = {Bhattacharjee, Debjyoti},
  year = {2015},
  school = {Indian Statistical Institute, Kolkata},
  link = {https://pdfs.semanticscholar.org/8fe0/04c6bffc468b7991f4f662f120ba8c0201aa.pdf}
}
```